7290-072011-1 features: ? controls bipolar and unipolar motors ? cost-effective replacement for l297 ? full, ? step mode selected with mode input ? direction control ? reset input ? step control input ? enable input ? pwm chopper circuit for current control ? two peak-current comparators with external reference input ? step control frequency and duty cycle controlled by an external frequency source or by an internal crystal controll ed oscillator (typically 8 mhz) ? all inputs and outputs ttl/cmos compatible (ttl for 5v operation) ? 3v to 5.5v operation (v dd ? v ss ) ? LS7290 (dip), LS7290-s (soic), LS7290-ts (tssop) ? see figure 1 . description: the LS7290 generates phase drive outputs and pwm outputs for controlling two- phase bipolar motors or four-phase un ipolar motors, respectively. the LS7290 contains a mode controlled look-up table for generating the motor duty cycle drive sequences. there are four outputs which are used to drive two h-bridges for the two motor windings in the bipolar motor or the fo ur driver transistors for the two center- tapped windings in the unipolar motor (refer to table 2). the LS7290 can step a motor in full steps and half steps. the refresh rate is set using an internal oscillator controlled by a crystal or by use of an exter nal input clock. typical refresh rate is equal to 31.25khz with the clock frequency set at 8mhz. peak-current feedback control using pulse-width modulation is used in full-step or half-step modes. the chopper consists of a voltage comparator, flip-flop and external se nse resistor. the internal oscillator sets the flip-flop and enables the inh1 and inh2 outputs at the beginning of each pwm cycle. once the peak motor current causes the voltage across the sense resistors to reach the voltage set by vref, the outputs ar e disabled until the next oscillator pulse. the vref voltage sets the peak current in each motor winding. input/output description reset input active low. resets the pwm table pointer to home position per table 2 and brings inh1 and inh2 low. upon power-up, a por circuit also resets the pwm table pointer. enable input active low. when high (inactive), brings ph a, phb, phc, phd, inh1 and inh2 outputs low. step input active low. a low-going pulse on this input causes the motor to advance one step. note: pins 2 and 3 are used for factory test and must be tied to ground. frd/rvrs input a low input causes the motor to move in incremental steps in reverse direction per table 2. a high input causes the motor to move in incremental steps in forward direction per table 2. switching directions can occur at any time. mode input defines the stepping modes as follows: mode full step mode 0 ? step mode 1 stepping mode can be changed at any time. sense1 / sense2 inputs inputs for motor winding current sense. a fractional-ohm resistor connected in series with each of the h-bridge drivers produce sense1 and sense2 voltages. these voltages are compared with vref voltage input, for generating the pwm inhibit outputs. stepper motor controller j uly 2011 LS7290 pin assignment top view figure 1.
7290-072011-2 vref input external voltage reference for chopper circuit which determines the maximum motor winding current by regulating the pwm duty cycle. the sense resistors should satisfy the equations r s1 = r s2 = v ref / i max where i max is the maximum motor winding current. r x , c x , clk these three pins can be configured in one of three ways to obtain the primary clock. a crystal connect ed between rx and clk pins or a resistor-capacitor pair connected among all three pins (see figure 4) can make use of the internal oscillator. alternatively, the clk pin can be driven from an external clock source. ds0/ds1 inputs the phase drive is blanked out between steps by switching outputs inh1 and inh2 low in order to reduce audible noise and power consumption. the duration of the blanking is selected by ds0 and ds1 according to table 1. ds1 ds0 blanking time, ipb, at f c = 8mz 0 0 1.25 s 0 1 2.50 s 1 0 3.75 s 1 1 5.00 s pha / phb / phc / phd outputs the state of these phase outputs are determined by the look-up table and are used to control either the left or right half of each of the h-bridge drivers. a low on a phase output enables the bottom driver while a high on the output enables the top driver. home output indicates step0 state per table 2 with a logic low. inh1 / inh2 outputs these outputs are used to provide pwm control to each of the two h-bridge drivers. table 1 the information included herein is be lieved to be accurate and reliable. however, lsi computer systems, in c. assumes no responsibilities for inaccuracies, or for any infringements of patent rights of others which may result from its use. figure 2. LS7290 block diagram
7290-072011-3 absolute maximum ratings: parameter symbol value unit dc supply voltage v dd - v ss +7 v any input voltage v in v ss ? 0.3 to v dd + 0.3 v operating temperature t a -20 to +85 c storage temperature t stg -85 to +150 c electrical specifications (-25 c < t a < +85 c) parameter symbol min typ max unit conditions supply voltage v dd 3.0 - 5.5 v - supply current i dd - - 2.0 ma outputs floating, inputs high clk frequency f c 8.0 - mhz - enable propagation delay t epd 100 - - ns - frd/rvrs setup time (before step pulse) t ds 0 - - s - step pulse width spw 1.0 - - s at f c = 8 mhz interstep pulse delay isd 32 - - s at f c = 8 mhz interstep phase blanking ipb 1.25 - 5.0 s at f c = 8 mhz reset pulse width r pw 1.0 - - s at f c = 8 mhz reset to step pulse delay t rs 0 - - s - hi-level input voltage v ih 2 - - v v dd = 5 0.25v low-level input voltage v il - - 0.8 v v dd = 5 0.25v high-level input current i h - - 50 na leakage current low-level input current i l - - 50 na leakage current output sink current i o -10 - - ma v o = 0.4v, v dd = 5v i o -5 - - ma v o = 0.4v, v dd = 3.3v output source current i o 5 - - ma v o = 4v, v dd = 5v i o 2.5 - - ma v o = 2.5v, v dd = 3.3v comparator offset voltage v os - 5 15 mv v ref = 1v input reference voltage v ref 0.5 - 3.0 v v dd = 5v v ref 0.5 - 1.5 v v dd = 3.3v fc ~ 1/5rc at vdd = 5v and r = 2.2 k , c = 12pf, oscillator frequency is 8 mhz (typical). figure 3. rc oscillator for clock generator
7290-072011-4 figure 4. partial sequence in forward half- step mode
7290-072011-5 figure 5. typical application schematic for a two phase bipolar motor using a single motor ic
7290-072011-6 figure 6. typical application schematic for a two phase bipolar motor using two separate motor driver ics
7290-072011-7 note: q1, q2, q3, q4 are mosfet power transistors suitable for 5v gate drive typical p/ns = irlz44n and irf3708 figure 7. typical application schematic for a four phase unipolar motor using discrete mosfet transistors
7290-072011-8 table 2 step number % duty cycle phases step angle full 1/2 inh1 inh2 pha phb phc phd 0 0 100 0 1 0 1 0 home 1 70.7 70.7 1 0 1 0 45 1 2 0 100 0 1 1 0 90 3 -70.7 70.7 0 1 1 0 135 2 4 -100 0 0 1 0 1 180 5 -70.7 -70.7 0 1 0 1 225 3 6 0 -100 1 0 0 1 270 7 70.7 -70.7 1 0 0 1 315 0 0 100 0 1 0 1 0 home figure 8. selecting between fast and slow decay for one stepper motor winding (use identi cal circuit for the othe r stepper motor winding) note: in fast decay mode, inhibit windings are chopped. in slow decay mode, phase windings are chopped. nor gates: cd4001 or gates: cd4071
7290-072011-9 z = 10v inverters = 74hc04 gates = 74hc08 q1 = q3 = irf6215 (typical) q2 = q4 = irli3615 (typical) figure 9. 120v motor discrete component driver
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